The present invention relates to phase interpolators.
Phase interpolation is a useful technique in the generation of repetitive waveforms, such as device clocks. In phase interpolation input clocks are supplied which are phase offset from each other to a phase interpolator. The phase interpolator then has the ability to adjust its output to any phase-angle between the input clocks. This technique is very useful in the area of delayed locked loops (DLLs) and phase locked loops (PLLs) as well as most delay-matching circuitry. Phase interpolation is particularly useful in the phase shifting circuit of FIG. 1.
Some conventional phase interpolators are susceptible to output jitter. For example, the phase interpolator described in U.S. Pat. No. 5,554,945 of Lee et al. (see FIG. 2) is strongly susceptible to output jitter when there is noise on the bulk bias supply Vbb. It would be desirable to have a phase interpolator that was less susceptible to output jitter when there is noise on a Vbb supply.
Some conventional phase interpolators also require that input vectors or clocks be very closely spaced. For example, the phase interpolator disclosed in A SEMI-DIGITAL DUAL DELAY-LOCKED LOOP, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, by Sidiropoulos and Horowitz, generally requires that the rise/fall times of the input waveforms must overlap for good interpolation. This often results in smaller frequency range if the interpolator is used in a PLL/DLL application, or a requirement for the generation of multiple very finely spaced input vectors. It would be desirable to have a phase interpolator that did not require the input vectors to be as closely spaced as in conventional designs.
A phase interpolator circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first control voltage and a first current mirror circuit to generate a second current that is based on the first current. The phase interpolator circuit further includes a first current steering switch to steer the second current to one of first and second nodes to generate a first voltage transition at one of the first and second nodes, the second current being steered to the first node when a first input signal is in a first state and to the second node when the first input signal is in a second state.
A phase interpolator with noise immunity is described. The phase interpolator includes a voltage-to-current conversion circuit that receives a differential voltage and generates a differential current. The differential current is mirrored and provided to a phase Max/Min detector circuit and current switches. The phase Max/Min detectors may generate signals for a phase selector circuit. The current switches provide the mirrored current to a phase comparator and a load circuit in response to input vectors and a quadrant select signal. The phase comparator generates output waveforms from the phase interpolator.
The present invention provides multiple advantages over conventional phase interpolators. This invention provides outputs with lower output jitter. One way this is done is via significantly better noise rejection, both from the Vbb and Vdd supply. This invention has much lower Vbb sensitivity than the phase interpolator of U.S. Pat. No. 5,554,945. It also has fewer stacked series devices, allowing for better Vdd noise rejection and operation at low supply voltages. The present invention also provides integrated interpolation waveforms of much higher quality. This minimizes jitter in what is normally the worst area, the low-swing to high-swing amplification of a comparator. This invention gives waveforms with larger swing and better dV/dT at the crosspoint. Providing better waveforms to the comparator minimizes jitter created by the low-swing to high-swing amplification.
This invention also uses the integration of current into capacitance instead of phase-blending to avoid the tight spacing requirement and has superior performance over Sidiropoulos et al. when presented with input clocks whose spacing is greater than their rise/fall time.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.